A Backscattering Model Incorporating the Effective Carrier Temperature in Nano MOSFET

In this work we propose a channel backscattering model in which increased carrier temperature at the top of the potential energy barrier in the channel is taken into account. This model represents an extension of a previous model by the same authors which highlighted the importance of considering the partially ballistic transport between the source contact and the top of the potential energy barrier in the channel. The increase of carrier temperature is precisely due to energy dissipation between the source contact and the top of the barrier caused by the high saturation current. To support our discussion, accurate 2D full band Monte Carlo device simulations with quantum correction have been performed in double gate nMOSFETs for different geometries (gate length down to 10 nm), biases and lattice temperatures. Including the effective carrier temperature is especially important to properly treat the high inversion regime, where previous backscattering models usually fail

A microscopically accurate model of partially ballistic nanoMOSFETs in saturation based on channel backscattering

We propose a model for partially ballistic MOSFETs and for channel backscattering that is alternative to the well known Lundstrom model and is more accurate from the point of view of the actual energy distribution of carriers. The key point is that we do not use the concept of "virtual source". Our model differs from the Lundstrom model in two assumptions: i) the reflection coefficients from the top of the energy barrier to the drain and from top of the barrier to the source are approximately equal (whereas in the Lundstrom model the latter is zero), and ii) inelastic scattering is assumed through a ratio of the average velocity of forward-going carriers to that of backward-going carriers at the top of the barrier kv > 1 (=1 in the Lundstrom model). We support our assumptions with 2D full band Monte Carlo (MC) simulations including quantum corrections in nMOSFETs. We show that our model allows to extract from the electrical characteristics a backscattering coefficient very close to that obtained from the solution of the Boltzmann transport equation, whereas the Lundstrom model overestimates backscattering by up to 40%

Modelling of tunnelling currents in Hf-based gate stacks as a function of temperature and extraction of material parameters

In this paper we show that through electrical characterization and detailed quantum simulations of the capacitance-voltage and current-voltage characteristics it is possible to extract a series of material parameters of alternative gate dielectrics. We have focused on HfO2 and HfSiXOYNZ gate stacks and have extracted information on the nature of localized states in the dielectric responsible for a trap-assisted tunneling current component and for the temperature behavior of the I-V characteristics. Simulations are based on a 1D Poisson-Schrdinger solver capable to provide the pure tunneling current and Trap Assisted Tunneling component. Energy and capture cross section of traps responsible for TAT current have been extracted.Comment: Preprint version of a paper submitted to TED, Transaction on Electron Devices. this is the final reviewed version. This work studies HfO2 and HfSiXOYNZ gate stacks, their C-V and I-V characteristics. A temperature dependent Trap Assisted Tunnneling model was developed to explain the temperature dependence of the I-V chaacteristic

Operation and physics of photovoltaic solar cells: an overview

Solar energy is considered the primary source of renewable energy on earth; and among them, solar irradiance has both, the energy potential and the duration sufficient to match mankind future energy needs. Nowadays, despite the significant potential of sunlight for supplying energy, solar power provides only a very small fraction (of about 0.5%) of the global energy demand. In order to increase the worldwide installed PV capacity, solar photovoltaic systems must become more efficient, reliable, cost-competitive and responsive to the current demands of the market. In this context, PV industry in view of the forthcoming adoption of more complex architectures requires the improvement of photovoltaic cells in terms of reducing the related loss mechanism, focusing on the optimization of the process design, as well as, reducing manufacturing complexity and cost. Hence a careful choice of materials, a suitable architecture and geometric distribution, passivation techniques and the adoption of a suitable numerical modeling simulation strategy are mandatory. This work is part of a research activity on some advanced technological solutions aimed at enhancing the conversion efficiency of silicon solar cells. In particular, a detailed study on the main concepts related to the physical mechanisms such as generation and recombination process, movement, the collection of charge carriers, and the simple analytical 1D p-n junction model required to properly understand the behavior of solar cell structures. Additionally, the theoretical efficiency limits and the main loss mechanisms that affect the performance of silicon solar cells are explained

Barrier Lowering and Backscattering Extraction in Short-Channel MOSFETs

In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate length down to 70 nm. Moreover we propose an extension of the backscattering model to the case of 2D geometries (e.g. bulk MOSFETs). We found that, in this case, the backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1D approach can be significantly different from the real 2D value

A Sub-kT/q Voltage Reference Operating at 150 mV

We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger than 4kT/q. The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for VDD ranging from 0.15 to 1.8 V is 359.5 μV/V, whereas the mean variation of VREF in the temperature range from 0°C to 120°C is 26.74 μV/°C. The mean power consumption at 25 °C for VDD = 0.15 V is 26.1 pW. The occupied area is 1200 μm2

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs).We propose a mixed TFET\u2013MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET\u2013MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET\u2013MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions

Understanding the Optimization of the Emitter Coverage in BC-BJ Solar Cells☆

Abstract In this work, by exploiting two-dimensional (2-D) TCAD numerical simulations, we performed a study of optimum emitter coverage ratio (R opt ) to reach maximum performance on back contact-back junction (BC-BJ) solar cells. R opt exhibits a strong dependence on pitch, emitter and back surface field (BSF) doping and bulk resistivity, ranging between 0.6 and 0.95. By fixing BSF doping, emitter doping and bulk resistivity, BSF and emitter width can be optimized independently one another. The optimum BSF width and the optimum emitter width are given by a trade-off between series resistance and electrical shading losses. From the design perspective, focusing on optimizing the BSF and emitter width is more effective than optimizing R at fixed pitch or BSF width

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III\u2013V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type I\u2013Vs, trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed

Analysis of the impact of doping levels on performance of back contact - back junction solar cells

AbstractIn this work, by exploiting two-dimensional (2-D) TCAD numerical simulations, we performed a study of the impact of the doping levels on the main figures of merit in the different regions of a crystalline silicon Back-Contact Back-Junction (BC-BJ) solar cell: the emitter, the Back Surface Field (BSF) and the Front Surface Field (FSF). The study is supported by a dark loss analysis which can highlight the contribution of several recombination mechanisms to the total diode saturation current. The efficiency curve as a function of doping level exhibits a bell-shape with a clearly identifiable optimum value for the three regions. The decrease in efficiency observed at lower doping values is explained in terms of higher contact recombination for BSF and emitter, and in terms of higher surface recombination for FSF. The efficiency decrease observed at higher doping values is ascribed to the higher surface recombination for FSF and Auger recombination for all cases